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021
CY7C1021
64K x 16 Static RAM
Features
* High speed -- tAA = 12 ns * CMOS for optimum speed/power * Low active power -- 1320 mW (max.) * Automatic power-down when deselected * Independent Control of Upper and Lower bits * Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021 is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ packages.
Functional Description
The CY7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
DATA IN DRIVERS
Pin Configuration
SOJ / TSOP II Top View A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A7 A6 A5 A4 A3 A2 A1 A0
64K x 16 RAM Array 512 X 2048
I/O1 - I/O8 I/O9 - I/O16
COLUMN DECODER BHE WE CE OE BLE
A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
1021-2
ROW DECODER
Selection Guide
7C1021-10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA)
Shaded areas contain preliminary information.
A8 A9 A10 A11 A12 A13 A14 A15
SENSE AMPS
7C1021-12 12 220 5 0.5
7C1021-15 15 220 5 0.5
7C1021-20 20 220 5 0.5
10 Commercial Commercial L 220 5 0.5
Cypress Semiconductor Corporation Document #: 38-05054 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised August 24, 2001
CY7C1021
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ......................................-0.5V to VCC+0.5V DC Input Voltage
[1]
Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
..................................-0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range
Test Conditions Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage VCC = Min., IOH = -4.0 mA Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current
[1]
7C1021-10 Min. 2.4 0.4 2.2 -0.5 6.0 0.8 +1 +1 -300 220 Max.
7C1021-12 Min. 2.4 0.4 2.2 -0.5 -1 -1 6.0 0.8 +1 +1 -300 220 Max.
7C1021-15 Min. 2.4 0.4 2.2 -0.3 -1 -5 6.0 0.8 +1 +5 -300 220 Max.
7C1021-20 Min. 2.4 0.4 2.2 -0.3 -1 -5 6.0 0.8 +1 +5 -300 200 Max. Unit V V V V A A mA mA
VCC = Min., IOL = 8.0 mA
GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC
-1 -1
ISB1
Automatic CE Max. VCC, Power-Down Current CE > VIH VIN > VIH or --TTL Inputs VIN < VIL, f = fMAX Automatic CE Max. VCC, Power-Down Current CE > VCC - 0.3V, --CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f=0 L
40
40
40
40
mA
ISB2
5 0.5
5 0.5
5 0.5
5 0.5
mA mA
Shaded areas contain preliminary information.
Capacitance[4]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05054 Rev. **
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CY7C1021
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255 R 481 R 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE 167 30 pF R2 255 GND < 3 ns 3.0V 90% 10% 90% 10% < 3 ns ALL INPUT PULSES
(a)
(b)
1021-3
OUTPUT Equivalent to: THEVENIN EQUIVALENT
1.73V
1021-4
Switching Characteristics[5] Over the Operating Range
7C1021-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z CE HIGH to High Z
[6, 7]
7C1021-12 Min. 12 Max.
7C1021-15 Min. 15 Max.
7C1021-20 Min. 20 Max. Unit ns 20 3 20 9 0 9 3 9 0 20 9 0 9 20 12 12 0 0 12 10 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 12 ns ns
Description
Min. 10
Max.
10 3 10 5 0 5 3 5 0 10 5 0 5 10 8 7 0 0 7 5 0 3 5 7 8 12 9 8 0 0 8 6 0 3 0 0 3 0 3
12 3 12 6 0 6 3 6 0 12 6 0 6 15 10 10 0 0 10 8 0 3 6 9
15 15 7 7 7 15 7 7
CE LOW to Low Z[6]
[6, 7]
CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z
[8]
WRITE CYCLE
Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z
[6, 7]
7
Byte Enable to End of Write
Shaded areas contain preliminary information. Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05054 Rev. **
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CY7C1021
Switching Waveforms
Read Cycle No. 1
[9, 10]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
1021-5
Read Cycle No. 2 (OE Controlled)
ADDRESS
[10, 11]
tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% IISB SB
1021-6
tHZOE
HIGH IMPEDANCE
DATA OUT
IICC CC
Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05054 Rev. **
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CY7C1021
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)
[12, 13]
tWC ADDRESS
CE
tSA
tSCE
tAW tPWE WE tBW BHE, BLE tSD DATA I/O tHD
tHA
1021-7
Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
BHE, BLE
tSA
tBW
tAW tPWE WE tSCE CE tSD DATA I/O tHD
tHA
1021-8
Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05054 Rev. **
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CY7C1021
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, LOW)
tWC ADDRESS
CE
tSCE
tAW tSA tPWE
tHA
WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD
1021-10
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H I/O1-I/O8 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z I/O9-I/O16 High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Power-Down Read - All bits Read - Lower bits only Read - Upper bits only Write - All bits Write - Lower bits only Write - Upper bits only Selected, Outputs Disabled Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Document #: 38-05054 Rev. **
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CY7C1021
Ordering Information
Speed (ns) 10 Ordering Code CY7C1021-10VC CY7C1021-10ZC CY7C1021L-10ZC 12 CY7C1021-12VC CY7C1021-12VI CY7C1021-12ZC 15 CY7C1021-15VC CY7C1021-15VI CY7C1021-15ZC CY7C1021-15ZI CY7C1021L-15ZC 20 CY7C1021-20VC CY7C1021-20ZC
Shaded areas contain preliminary information.
Package Name V34 Z44 Z44 V34 V34 Z44 V34 V34 Z44 Z44 Z44 V34 Z44
Package Type 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead TSOP Type II 44-Lead (400-Mil) Molded SOJ 44-Lead TSOP Type II
Operating Range Commercial Commercial Commercial Commercial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Commercial Commercial
Package Diagrams
44-Lead (400-Mil) Molded SOJ V34
51-85082-B
Document #: 38-05054 Rev. **
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CY7C1021
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
Document #: 38-05054 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1021
Document Title: CY7C1021 64K x 16 Static RAM Document Number: 38-05054 REV. ** ECN NO. 107156 Issue Date 09/10/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00224 to 38-05054
Document #: 38-05054 Rev. **
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